实现一种基于FPGA的Turbo译码器实验平台,包括译码数学模型、FPGA实现方案、测试结果及分析。系统采用一个通用硬件平台和模块化的软件设计,可对译码算法和迭代次数进行可视化设置。通过仿真与实际测试,结果正确且工作稳定可靠。
Abstract
This paper presents a design of a Turbo decoder experimental platform based on a
fieldprogrammable gate array (FPGA), including mathematical models of the dec
oder, realization of the program based on the FPGA, and analysis of test results
. The system is based on a general hardware platform and modular software design
and provides visualization of the settings of the decoding algorithms and itera
tions. Simulations and actual tests show that the decoder meets the design requi
rements of stability and reliability.
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参考文献
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脚注
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